Conventionally, there is known a coreless wiring substrate having a predetermined number of insulating layers and wiring layers alternately layered one on top of the other. The wiring substrate has one surface on which a semiconductor chip is mounted (semiconductor chip mounting surface) and another surface to which an external connection terminal is bonded (external connection terminal bonding surface). Among the insulating layers of the wiring substrate, glass cloth is included in the insulating layer that includes the external connection terminal bonding surface and is not included in the other insulating layers. The insulating layers that do not include the glass cloth are formed of the same insulating resin and are adjusted to have substantially the same thermal expansion coefficient (see, for example, Japanese Laid-Open Patent Publication No. 2009-224739).